SI = Super Intelligence × System Integration

把 AI 可靠地接進
真實的機台、流程與硬體。 Reliably integrating AI into real machines, processes and hardware.

我是 Plus，半導體封裝與測試／智慧工廠的專業經理，也是重度 AI builder。本業做良率、RCA、PdM 與 NPI；在本業之外，我動手做 Physical AI、agent 可靠執行（harness / eval / memory）與地端 LLM。 I'm Plus, a semiconductor packaging & test / smart-factory manager and a hands-on AI builder. My day job is yield, RCA, PdM and NPI. Beyond it I build Physical AI, reliable agent execution (harness / eval / memory) and on-prem LLM systems.

看代表作品See flagship projects → 認識我About me

SI 是雙關：2026 年 9 月美國行政命令改用「Super Intelligence (SI)」稱呼 AI；在台灣，SI 一直是 System Integration。這個網站做的就是兩者的交集。 SI is a double meaning: a September 2026 US executive order adopted "Super Intelligence (SI)" in place of AI, while in Taiwan SI has long meant System Integration. This site lives at their intersection.

SYS-INT / v0SCHEMATIC

L3 Models & Agents LLM · multi-agent · local vLLM

L2 整合層 IntegrationIntegration layer MCP tools · safety gates · eval · evidence

M機台MachinesSO-ARM101

P流程ProcessesRCA · PdM

H硬體HardwareESP32-S3

M / Machines

以 restricted MCP tools 控制機械手臂，硬體實測，動作需明確授權。Robot arm driven through restricted MCP tools, verified on hardware, with explicit motion authorization.

P / Processes

10-agent 良率 RCA pipeline 端到端建置完成（內部）；設備無關 PdM Playbook v1.0。10-agent yield RCA pipeline built end-to-end (internal); equipment-agnostic PdM Playbook v1.0.

H / Hardware

兩台 ESP32-S3 桌面 AI 助理：STT、LLM、TTS、伺服，自架 server，實機驗收。Two ESP32-S3 desktop AI assistants: STT, LLM, TTS and servos on a self-hosted server, hardware-verified.

專業：半導體 × AIWork: Semiconductor × AI

可公開版的方法論。全部去識別化：不含公司、客戶、機台編號或實際數據。Public-safe methodology. Fully de-identified: no employer, customer, tool IDs or production data.

RCAObservable → Root Cause → Action 診斷矩陣Observable → Root Cause → Action diagnostic matrices
PdM第一性原理 + 資料側優先的健康監測方法First-principles, data-side-first health monitoring
SOP→AGENT把人類 SOP 轉成可治理的 agentic workflowTurning human SOPs into governed agentic workflows
ADOPTION企業 AI roadmap、訓練、地端 LLM 導入經驗Enterprise AI roadmap, training and on-prem LLM adoption

［待補］首批 2 篇專業文章連結[TBD] Links to the first two methodology articles

作品：代表作Projects: Flagships

每個成熟度標籤都對應一份證據；還沒有證據的就照實標成 Pending。Each maturity label is backed by evidence. Anything without evidence yet is labelled Pending.

Live Hardware verified Built Prototype Research in progress Concept

F-01Hardware verified

AI-collaborative Physical AI Lab

SO-ARM101 · LeRobot · MCP

以 restricted MCP tools（status / wave / stop）、多相機 vision 與 fail-closed 安全 gate，把 agent 接到 SO-ARM101 leader/follower 機械手臂。Agents connected to SO-ARM101 leader/follower arms through restricted MCP tools (status / wave / stop), multi-camera vision and fail-closed safety gates.

已驗證Verified: 組裝、calibration、bounded teach-in、MCP wave 實機Assembly, calibration, bounded teach-in, MCP wave on hardware
待完成Pending: ACT 訓練、自主 pick-and-placeACT training, autonomous pick-and-place

F-02Built · Method v1.0

A&T PdM Playbook

PdM · RCA · SPC

設備無關的 PdM／健康監測方法論：七步 pipeline，搭配 Observable → Root Cause → Action 診斷矩陣。Equipment-agnostic PdM / health-monitoring methodology: a seven-step pipeline with Observable → Root Cause → Action diagnostic matrices.

已套用Applied to: 兩類設備：Prober、Die BonderTwo equipment types: prober, die bonder
公開範圍Public scope: 只公開方法論與合成範例Method and synthetic example only

F-03Built (internal)

Semiconductor RCA Multi-Agent Governance

Multi-agent · vLLM · Governance

10-agent wafer-test 良率 RCA pipeline 的治理設計：stage-gate、deterministic evidence chain、model-external policy、human escalation 與 audit。Governance design for a 10-agent wafer-test yield RCA pipeline: stage gates, a deterministic evidence chain, model-external policy, human escalation and audit.

狀態Status: 內部端到端建置完成，非公開Built end-to-end internally; not public
公開形式Public form: 架構圖 + 合成資料 walkthrough（Pending）Architecture + synthetic walkthrough (Pending)

F-04Research in progress

Visual-in-the-Loop Debugging

Agent eval · ESP32-S3 · Camera

研究問題：外部相機加上 Serial telemetry，能不能幫 AI agent 抓出並修好「編譯成功、實體行為卻錯」的韌體 bug？Can external-camera evidence plus Serial telemetry help an AI agent find and fix firmware faults that compile but misbehave in the physical world?

已完成Done: 論文 Draft v0.1、4 種 baseline 設計、24 類 fault taxonomyPaper draft v0.1, four baselines designed, 24-fault taxonomy
結果Results: Pending

// LAB — 更多作品More builds

L-05Hardware verified

StackChan Desktop AI Assistant

兩台 ESP32-S3：本地 STT、雲端 LLM（六種情緒）、TTS 嘴型同步、伺服頭部，自架 WebSocket server。Two ESP32-S3 units: local STT, cloud LLM with six emotions, lip-synced TTS and servo head on a self-hosted WebSocket server.

L-06Live

MFG AGI Dashboard

給封測（OSAT）工程師的 AI 助理入口，Claude API，部署於 Vercel。AI assistant portal for OSAT manufacturing engineers, built on the Claude API and deployed on Vercel.

L-07Prototype

MemoryArk

本機加密備份並搜尋 Claude Code／Codex／Cursor 的 session：AES-256-GCM、SQLite FTS5、本地 embedding。Local encrypted backup and search of Claude Code / Codex / Cursor sessions: AES-256-GCM, SQLite FTS5, local embeddings.

L-08Built

Agent-native Second Brain

讓 AI agent 能穩定維護的 Obsidian 知識庫：規則檔、OKF frontmatter、MOC／index、git 安全邊界。An Obsidian knowledge base AI agents can maintain reliably: rule files, OKF frontmatter, MOC / index, git safety boundaries.

L-09Live

3D & Interactive Wall

Three.js 街區重建、Microduck 3D 組裝 explorer、SolarSystem 等 AI 協作開發作品。Three.js neighborhood reconstruction, Microduck 3D assembly explorer, SolarSystem and more, built with AI collaboration.

關於About

我的工作方法：先建可複用的框架，再套到個案；用 gate 制驗收，完成就要拿得出證據；卡住的地方照實標出來。半導體 domain knowledge 是我做 AI 的優勢，AI 也反過來讓本業更深。How I work: build reusable frameworks before individual cases, accept work through gates, back every "done" with evidence, and flag blockers honestly. Semiconductor domain knowledge is my edge in AI, and AI in turn deepens my domain work.

［待決定］對外公開姓名、所在地、履歷 PDF[TBD] Public name, location, resume PDF

Google Cloud Digital Leader
Google Generative AI Leader
Six Sigma
內部稽核員Internal Auditor
專案管理Project Management

把 AI 可靠地接進真實的機台、流程與硬體。 Reliably integrating AI into real machines, processes and hardware.